As integrated circuits become faster and denser, requirements for lithography become increasingly stringent. Errors in lithography can result from in-the-plane distortions (which can result in overlay errors) or from out of the plane distortions, which can result in defocus. The necessity for verifying that a given wafer is sufficiently planar and within specifications, i.e. in qualifying and selecting wafers even before processing begins or during processing, is becoming ever greater. A critical component in the characterization of wafers is the wafer topography, sometimes termed substrate geometry.
Wafer topography (i.e., substrate geometry) can be described according to traditional parameters such as shape, thickness/flatness, and nanotopography (NT). These parameters have different characteristics, as is illustrated in FIG. 1a. The data representing these parameters have a high spatial resolution of about 0.2 mm. Shape is defined as the median surface of the substrate (as in the deviation of the median surface from a reference plane), generally in a free state, and is a low frequency component of the wafer. Shape is characterized by global metric such as warp and bow. Flatness is defined as the thickness variation of a substrate with the back surface assumed to be completely flat, and is characterized by metrics, which may be localized or site-based. Characterization and quantification of higher order components of shape and more localized shape features are described in PCT publication No. WO 2010/025334, and U.S. Provisional application No. 61/092,720, both of which are incorporated by reference in their entireties. The impacts of the wafer shape on lithography parameters are described in K. Turner et al, “Predicting Distortions and Overlay Errors Due to Wafer Deformation During Chucking on Lithography Scanners”, J. Micro/Nanolith, MEMS MOEMS 8(4), 043015, (October-December 2009), and the impacts of flatness on lithography parameters are described in J. Valley et al, “Approaching New Metrics for Wafer Flatness: An Investigation of the Lithographic Consequences of Wafer Non-Flatness”, Proceedings of SPIE, 5375, 1098 (2004) which is hereby incorporated by reference in its entirety.
In particular, higher order components of wafer shape and NT, as illustrated in FIG. 1b, might influence both overlay, i.e. registration or alignment between lithography levels, and defocus. Nanotopography is the high frequency component of the front and back surface of the substrate, defined as being in a spatial wavelength regime of 0.2-20 mm, and with a feature height of a few nanometers. NT may occur as point defects (e.g., dimples, epi defects such as pins or crowns, bumps such as notches or lasermarks) or as line defects (e.g., saw marks from slicing, scratches, slip lines, dopant striation or other process signatures). The individual front/back surface nanotopography of a wafer substrate is typically obtained from the front/back topography by applying high pass filtering schemes such as Double Gaussian (DG) filtering to the topography data, which suppresses the low frequency components of the wafer topography. The substrate NT parameters are seen to affect the lithography process, for example by contributing to defocus and overlay errors.
Typically, in lithographic processing, corrections to distortions or other topographic features which may result in overlay or defocus errors are applied by the scanner on both a full wafer-level and a site-by-site basis. The most common linear scanner corrections (which includes both wafer level and site level) for overlay are: translation in x and y, rotation, and site-level magnification in xy and y. The corrections in x and y typically have the mathematical form:dx=Δx−Δθ·y+MX·x dy=Δy−Δθ·x+MY·y where Δx and Δy are the shifts in x and y, Δθ is the rotation correction, and MX and MY are the magnification corrections in x and y. The corrections are typically calculated by minimizing the errors at target locations within the lithography sites using a process such as least squares.
Scanner based linear corrections can generally correct for lower order linear components of the substrate geometry and other linear components which might result in overlay and defocus errors. However, typically the lithography scanner has limited capability to correct for features with spatial frequency less than 1/slit size of the lithography scanner. The NT which has spatial frequency less than 1/slit size may therefore result in Non-Correctable Errors (NCE).